1. Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more specifically to a novel method for forming polycide (polysilicon/tungsten silicide) contacts or interconnections, and more specifically a method for making self-aligned contacts to field effect transistors (FETs). This novel method eliminates polycide notching at the edges of contacts when the patterned polycide layer is misaligned over the contact openings which would otherwise cause high leakage current and low device yields.
2. Description of the Prior Art
The integrated circuit density on semiconductor substrates has dramatically increased in recent years. This increase in density is a result of downscaling of the individual devices built in and on the substrate, and the increase in line pitch (reduced line widths and spacing between lines) of the interconnecting electrically conducting lines that are used to wire up the devices. Future requirements for even greater device packing density are putting additional demands on the photolithographic resolution and anisotropic plasma etching techniques. Additional demand is also being placed on more aggressive design ground rules that can unfortunately result in misalignment of one patterned level over another underlying patterned level, such as metal lines over contact openings.
One processing area where this misalignment is of particular concern is the alignment of a patterned polycide (second polysilicon/silicide) layer over the self-aligned contacts to the substrate for FETs having gate electrodes made from a patterned first polycide or polysilicon layer. This is best understood with reference to a conventional prior art structure as shown in FIGS. 1 and 2. Shown in FIG. 1 is a schematic elevational view of two closely spaced FET gate electrodes, labeled 5 and 7, formed from a first polysilicon or polycide layer on a portion of a substrate 10. A self-aligned opening 8 is then etched in an interlevel dielectric insulating layer 6 over the gate electrodes. The contact opening 8 extends over the gate electrodes 5 and 7 thereby forming the self-aligned contact 9 in opening 8 which, in this specific application, serves as a common contact to the shallow junction (e.g., source/drain) contact areas 18 between the gate electrodes 5 and 7 of the FETs. A polycide (polysilicon/silicide) layer 9 is deposited and patterned using conventional photolithographic techniques and anisotropic plasma etching to form the electrical contact and/or next level of interconnections to the source/drain area 18 in the contact opening 8. However, because of the tight ground rules, misalignment can occur resulting in the edge B of patterned layer 9 being coincident with the edge of the contact opening 8. For example, this can occur on static random access memory (SRAM) having minimum feature sizes of 0.35 micrometers (um) and a misalignment of only 0.15 um. When this misalignment occurs the anisotropic plasma etching of layer 9 at the steep step in the contact opening 8 in layer 6 can result in enhanced lateral erosion or notching of the second poly-silicon layer, as depicted as region A in FIG. 1.
To better depict the nature of the notching problem, a schematic cross-sectional view through region 2--2' of FIG. 1 is shown in FIG. 2 for a conventional FET structure. Briefly, the gate electrodes 5 and 7 for the FET structures are formed by patterning a first polysilicon or polycide layer. Lightly doped source/drain regions are formed adjacent to the gate electrodes by ion implantation and then insulating sidewall spacers (not shown in FIG. 1) are formed on the sidewalls of the gate electrodes 5 and 7. A second ion implant is used to form the heavily doped shallow contact areas 18 to complete the FETs. Next an insulating layer 26 is deposited and typically planarized to form an interlevel dielectric layer (ILD) over the FETs. Now to achieve the device high packing density and improved circuit performance, self-aligned contact openings 8 are etched in layer 26 extending over the gate electrodes 5 and 7, as shown in FIG. 1. As shown in FIG. 2, a second polysilicon layer 28 having a silicide layer 30 is deposited and patterned by anisotropic etching to form the polycide contact 9 or the next level of electrical interconnections to the contact areas 18 on the substrate.
Also shown in FIG. 1 are two adjacent contact openings 8' and 8" having respective polycide contacts 9' and 9" . It is desirable in the semiconductor industry to place the contacts as close as the photoresist resolution and alignment tolerances will allow to achieve the highest circuit density on the chip.
However, as more aggressive ground rules are used for patterning the polycide (polysilicon/silicide) layer 9, misalignment can result causing the edge of the patterned polycide layer 9 to be coincident with the edge of the contact opening 8, as shown in FIG. 1 and as depicted in the cross sectional view of FIG. 2. Unfortunately, during patterning, this results in notching or lateral erosion in the patterned second polysilicon layer 28 under the tungsten silicide layer 30, as depicted by the region A in FIGS. 1 and 2. This notching can result in plasma etch damage to the exposed portions of the shallow contact area 18 under the notch region A, resulting in higher leakage current between the contact 18 and substrate 10, leading to functional circuit failure, lower product yield, and reliability problems.
Several methods have been described in the prior art for improving contacts to the source/drain contact areas on FETs, but do not directly address the concerns cited above. For example, R. Lee et al., in U.S. Pat. No. 5,306,951, describe a method for making polysilicon structures, such as bit lines on memory devices in which a silicide is formed on the sidewalls to improve the conductivity. Another method is described by N. Godinho et al., in U.S. Pat. No. 5,483,104 in which a titanium silicide layer is formed on the gate electrode and the source/drain contacts, and a rapid thermal anneal is carried out in ammonia to convert the TiSi to a stable TiSi.sub.2 phase and to form a titanium nitride on the surface. This serves as a protective etch stop over the source/drain contact areas when the second polysilicon layer is patterned to form the next level of interconnections (e.g., bit lines). A titanium silicide is then formed after the polysilicon is patterned. S-G Wuu et al., U.S. Pat. No. 5,547,892, teach a method for forming novel plug structures to a polysilicon layer for thin film transistors (TFT) on SRAM devices and concurrently to the substrate, but do not describe contacts to the FET self-aligned source/drain contact areas. H. Yen et al., U.S. Pat. No. 5,510,296, teach a method for making non-self-aligned contacts to source/drain contact areas in which a tungsten silicide (WSi.sub.2) is formed on an amorphous polysilicon. The WSi.sub.2 /amorphous polysilicon is then etched and afterwards annealed to form the contact. B-J Woo et al., U.S. Pat. No. 4,774,201, provide a method for protecting the tungsten silicide from forming a rough surface on the gate electrode with a CVD oxide during a reoxidation. This reoxidation improves the gate oxide breakdown voltage at the edge of the gate electrode. Woo et al. do not address the formation of self-aligned source/drain contacts to the FETs.
Therefore, there is still a need in the semi-conductor industry to provide a method for etching polycide contacts or interconnections over contact openings to shallow junction contact regions on the substrate, and more particularly for etching self-aligned contacts to contact areas of FETs while eliminating or minimizing the notching.